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For information on testing DS1 links 
The DS-1 interface operates at 1.544 Mbps
over UTP-3 cables, compliant with ATM Forum UNI specifications.
It supports both PLCP and direct cell mapping and complies with
the following standards: ANSI T1.403-1989, AT&T TR62411,
CCITT G.704 and G.706. The interface has RJ45 connectors.
The pin assignments of the standard DS-1
UTP cable are as follows:
| Pin |
Straight Cable |
Cross Cable |
| 1 |
Tx- (ring) |
Rx- (ring) |
| 2 |
Tx+ (tip) |
Rx+ (tip) |
| 4 |
Rx- (ring) |
Tx- (ring) |
| 5 |
Rx+ (tip) |
Tx+ (tip) |
Pins 3, 6, 7 and 8 are not used.
The DS-1 frame is 193 bits long. The first
bit (F-bit) is used for overhead. The remaining 192 bits comprise
8 bits of payload from each of 24 users. Twelve frames are transmitted
together as a Superframe (SF); 24 frames may be transmitted
together as an Extended Superframe (ESF).
The structure of a DS-1 frame is shown in
the following illustration:
1
bit
<---> |
Payload
192 bits
<-------------------------------------------------------------------------------->
|
| F |
8 bits user
1 |
8 bits user
2 |
8 bits user
3 |
. . . |
8 bits user
24 |
DS-1
frame structure |
One frame may be transmitted every 125 microseconds.
Thus, a superframe (12 frames) requires 1.5 milliseconds. An
extended superframe (24 frames) requires 3.0 milliseconds for
transmission. The net transmission rate is 1.391 Mbits/sec.
Direct Mapping
When direct mapping framing mode is used,
cell delineation is used to locate the cell boundaries. Cell
delineation is the process of framing to ATM cell boundaries
using the header error checksum (HEC) field found in the ATM
cell header. The HEC is a CRC-8 calculation over the first 4
bytes of the ATM cell header. When performing delineation, correct
HEC calculations are assumed to indicate cell boundaries.
An initial bit by bit search is made for
a correct HEC sequence (HUNT state). Once located, the particular
cell boundary is noted (PRESYNC state) and the search continues
to determine whether the following pattern is correct. Once
no incorrect HEC is received within a set number of cells, the
SYNC state is declared. In this state, synchronization is not
relinquished until a set number of consecutive incorrect HEC
patterns are received.
PLCP
The PLCP frame is octet aligned to the framing
bit in the DS-1 frame. There is no relationship between the
start of the PLCP frame and the start of the DS-1 frame. A 6-byte
trailer is inserted at the end of each PLCP frame.
The DS-1 PLCP frame provides the transmission
of ten ATM cells every 3 msec. The net transmission rate is
thus 160 Kbytes/sec.
| A1 |
A2 |
P9 |
Z4 |
ATM Cell |
|
| A1 |
A2 |
P8 |
Z3 |
ATM Cell |
|
| A1 |
A2 |
P7 |
Z2 |
ATM Cell |
|
| A1 |
A2 |
P6 |
Z1 |
ATM Cell |
|
| A1 |
A2 |
P5 |
F1 |
ATM Cell |
|
| A1 |
A2 |
P4 |
B1 |
ATM Cell |
|
| A1 |
A2 |
P3 |
G1 |
ATM Cell |
|
| A1 |
A2 |
P2 |
M1 |
ATM Cell |
|
| A1 |
A2 |
P1 |
M2 |
ATM Cell |
|
| A1 |
A2 |
P0 |
C1 |
ATM Cell |
Trailer |
| <----------------> |
<---> |
<----------------> |
<---------------> |
| Framing |
POH |
53 Octets |
6 Octets |
DS-1
frame structure - PLCP cell mapping |
A-bits
Framing pattern octet.
P-bits
Path overhead identifier.
C-bit
Pad bit counter.
M-bits
SIP layer 1 management information.
G-bit
PLCP path status.
B-bit
Bit-interleaved parity 8 (BIP-8).
F-bit
PLCP path user channel.
Z-bits
For future use.
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