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For information on testing E1 links
The E1 interface operates at 2 Mbps over
coax cables, compliant with ATM Forum UNI specifications. It
supports both PLCP and direct cell mapping and complies with
the following standards: G.704, G.706, G.732. The interface
has BNC connectors.
The E1 transmission link consists of 32 transmission
channels (0-31), each of which is 64 Kbits/sec. The overall
transmission rate is 2.048 Mbits/sec. Channels 0 and 16 are
reserved for transmission management, while all other channels
are used for payload. The payload bandwidth is thus 1.920 Mbits/sec.
Since ATM uses 48 out of the possible 53 bytes for payload transmission,
the net transmission rate becomes 1.738 Mbits/sec.
Channel 0 carries F3-OAM information, signals
loss of frame or synchronization, and is responsible for transferring
FERF and LOC messages. Channel 16 is reserved for signalling.
Direct Mapping
The direct mapping of ATM cells onto E1 transmission
frames is specified in CCITT recommendation G.804. This specifies
that ATM cells are to be carried in bits 9-28 and 137-256 (corresponding
to channels 1-15 and 17-31).
The following is an illustration of the E1
frame format when direct mapping of ATM cells is used. The 53
byte ATM cell begins with a header and wraps around consecutive
E1 frames.
| Channel 0 |
Channel 16 for signalling |
| 256 bits/125 µsec |
| <--------------------------------------------------------------------------------------> |
| |
Header |
|
|
| |
|
|
|
| |
Header |
|
|
| |
|
|
Header |
| Channels 1-15 |
Channels 17-31 |
| <-----------------------------------> |
<-----------------------------------> |
E1 frame structure - direct mapping
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PLCP Cell Mapping
The PLCP format for E1 is described in ETSI
document ETS 300 213, where an E1 PLCP frame is specified as
consisting of ten rows of 57 bytes each. Four bytes are added
to the cell length of 53 bytes to provide the various overhead
functions.
The E1 frame structure with PLCP cell mapping
is illustrated in the following diagram:
| 1
<--> |
1
<--> |
1
<--> |
1
<--> |
53 bytes
<--------------------------------------------------------->
|
| A1 |
A2 |
P9 |
Z4 |
First
ATM Cell |
| A1 |
A2 |
P8 |
Z3 |
ATM
Cell |
| A1 |
A2 |
P7 |
Z2 |
ATM
Cell |
| A1 |
A2 |
P6 |
Z1 |
ATM
Cell |
| A1 |
A2 |
P5 |
F1 |
ATM
Cell |
| A1 |
A2 |
P4 |
B1 |
ATM
Cell |
| A1 |
A2 |
P3 |
G1 |
ATM
Cell |
| A1 |
A2 |
P2 |
M2 |
ATM
Cell |
| A1 |
A2 |
P1 |
M1 |
ATM
Cell |
| A1 |
A2 |
P0 |
C1 |
Last
ATM Cell |
E1
frame structure -PLCP cell mapping |
A-bits
Separator bytes.
P-bits
Path overhead identifier.
C1
Pad bit counter.
M-bits
SIP layer 1 management information.
G1
PLCP path status.
B1
Bit-interleaved parity 8 (BIP-8).
F1
PLCP path user channel.
Z-bits
For future use.
Thirty of the available 32 E1 channels are
used for transporting the PLCP frame. The remaining two channels
are reserved for E1 framing and signalling functions. The PLCP
frame is octet aligned to the channel boundaries in the E1 frame;
thus the A1 octet of the first row of the PLCP frame is inserted
into time slot 1 of the E1 frame.
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